`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/02/24 20:59:17
// Design Name: 
// Module Name: flowing_light
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module flowing_light(clk,rst_n,led);
    input clk;
    input rst_n;
    output reg [3:0] led;

    parameter   led_0 = 4'b0001,
		        led_1 = 4'b0010,
		        led_2 = 4'b0100,
		        led_3 = 4'b1000;
    parameter   T  = 50_000_000;

   

    reg [1:0]  st_now ;
    reg [1:0]  st_next;
    reg [25:0] cnt;
    always @(posedge clk or negedge rst_n) 
    begin
        if (!rst_n)
		begin
            cnt <=1'b0 ;
			st_now <= led_0;
			end
        else
		begin
             cnt <= cnt+1 ; 
			 st_now <= st_next;
		end 
    end
	
    always@(*)
 	begin	
        if(!rst_n)
			st_now=led_0;
	else
		case(st_next)
			led_0: begin
								if(cnt == T - 1)         
									st_now = led_1;
								else
									st_now = led_0;
							end
			led_1: begin
								if(cnt == T - 1)
									st_now = led_2;
								else
									st_now = led_1;
							end
			led_2: begin
								if(cnt == T - 1)
									st_now = led_3;
								else
									st_now = led_3;
							end
			led_3: begin
								if(cnt == T - 1)
									st_now = led_0;
								else
									st_now = led_3;
							end
			default:    ;
      endcase
end

always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
		led <= 4'b0001;
	else
		case(st_next)
			led_0: led <= 4'b0001;
			led_1: led <= 4'b0010;
			led_2: led <= 4'b0100;
			led_3: led <= 4'b1000;
			default   :               ;
		endcase

end

endmodule
                        
